Home – Home – Jornals – Avtometriya 2024 number 4

The results on the miniaturization of silicon-on-insulator (SOI) structures and SOI elements of integrated circuits (IC) are presented. To increase the IC performance, it is necessary to increase barriers and pulling electric fields due to high-k dielectrics and nanoscales, which lead to a noticeable decrease in the mobility of charge carriers with a decrease in the channel length and thickness. This, along with an increase in leakage due to source-drain tunnel currents, limits the physical length of the channel to 10 nm even when replacing silicon with two-dimensional (2D) materials such as graphene and metal dichalcogenides [1]. Three-dimensional (3D) integration in the form of double-gate transistors with complete depletion in SOI structures with a high-k buried dielectric (h- k BOX), in the form of the so-called fin transistors (FinFET) with two to four (gate-all-around ─ GAA) gates and channels of nanowires (NW FET), nanosheets (NS FET), nanoforks (FS FET), 2D materials and their 3D packaging allows one to increase the number of transistors on the chip, but not their performance. As an alternative, the option of increasing the functionality of the elements is considered, by replacing dielectrics in capacitors and transistors with ferroelectrics, and resistors with memristors, which leads to a transition from binary to neuromorphic logic, as well as to the implementation of the principles of radiophotonics, quantum devices, and sensors with parallel processing. A dynamically adjustable threshold and polarization of the gate ferroelectrics of complementary MOSFETs in heterosystems on a chip (SoC) will preserve ultra-low power consumption.